The rapid spread and sophistication of portable electronic apparatus commonly using microprocessors and complex monolithically integrated systems has made current consumption critical. That is energy consumption of battery powered portable apparatus is a concern. From a technological point of view, a response to the demand for reduced energy consumption is substantially that of further increasing the density of integration. In other words, as size reduction of individual integrated structures is performed, sub-micron dimensions have become half-micron dimensions. Of course, the scaling down process also includes reducing the supply voltage which permits a significant energy savings.
The scaling down process has strong repercussions on certain processing steps, referred to as the "front end" of the fabrication process. In traditional integration architectures, maintaining a high degree of flatness is fundamental in alleviating the criticality of successive masking steps. Along these lines, isolation areas among the distinct integrated structures may be advantageously realized by cutting trenches in the silicon that are then filled with dielectric materials. Other integration architectures, such as USLI (Ultra Large Scale Integration), may benefit from the possibility of cutting extremely precise and controlled trenches in a silicon monocrystal or in a polysilicon layer.
According to known techniques, such trenches are produced by anisotropic etching through the apertures of a resist mask, typically using Reactive Ion Etching (R.I.E.) techniques. These techniques have the disadvantage of being based on the etching time in the absence of appropriate markers to halt the etching once a predefined depth is reached. Moreover, the use of special gas mixtures of reactive compounds may leave undesired residues on the etched surface.